(1) Field of the Invention
The present invention relates to split-gate memory cells used in flash EEPROMs (Electrically Erasable Programmable Read Only Memories), and in particular, to a novel process for forming a flash memory cell.
(2) Description of the Related Art
A flash memory cell provides, with the use of a floating gate, nonvolatility to what is intrinsically volatile with the metal-oxide semiconductor (MOS) technology that is widely used in the semiconductor memory industry of today. As is well known, the term “flash” refers to the fact that the contents of the whole memory array, or of a memory block (sector) is erased in one step. The speed with which a memory cell can be programmed and erased is determined to a large extent by the geometrical shape and the dimensional characteristics of the floating gate as well as by the properties of the surrounding dielectric material that help retain the programmed information (charge) in the floating gate for extended periods of time. It is important, therefore, to be able to form cells with superior qualities for speed and retention of data, and it is for this purpose that a new method for forming flash memory cell is disclosed in the present invention.
Conventionally, and as is described more fully below, the floating gate of a split gate memory cell is formed by growing polysilicon oxide, or, polyoxide, on the polysilicon layer that eventually becomes the floating gate while the overlying polyoxide is used as a hard mask to etch the polysilicon gate. However, depending upon the doping, grain size and the oxidation speed of the polysilicon, there is formed around the edges of the polyoxide a protrusion of a particular shape, usually variations on the well known gate bird's beak, into the polysilicon which affects the erase speed of the cell and hence the performance of the memory device. Normally, the floating gate assumes a bulbous shape around the edges, which in turn adversely affects the speed of the cell. A different technique of forming the oxide over the polysilicon gate is proposed in this invention so that the edge of the underlying floating gate is well-defined and the speed of the cell is improved. The disclosed method also provides an improved alignment tolerance between the floating gate and the active region of the cell.
Memory devices include electrically erasable and electrically programmable read-only memories (EEPROMs) of flash electrically erasable and electrically programmable read-only memories (flash EEPROMs). Many types of memory cells for EEPROMs or flash EEPROMs may have source and drains regions that are aligned to a floating gate or aligned to spacers. When the source and drain regions are aligned to the floating gate, a gate electrode for a select transistor is separate from the control gate electrode of the floating gate transistor. Separate select and control gates increase the size of the memory cell. If the source and drain regions are aligned to a spacer formed after the floating gate is formed, the floating gate typically does not overlie portions of the source and drain regions. Programming and erasing performance is degraded by the offset between the floating gate and source and drain regions.
Most conventional flash-EEPROM cells use a double-polysilicon (poly) structure of which the well known split-gate cell is shown in FIGS. 1g. The forming of the cell is shown in FIGS. 1a-1f which will be described shortly. In the final form of the cell shown in FIG. 1f, a MOS transistor is formed on a semiconductor substrate (10) having a first doped region (11), a second doped region (13), a channel region (15), a gate oxide (30), a floating gate (40), intergate dielectric layer (50) and control gate (60). Substrate (10) and channel region (15) have a first conductivity type, and the first (11) and second (13) doped regions have a second conductivity type that is opposite the first conductivity type.
As seen in FIG. 1f, the first doped region, (11), lies within the substrate. The second doped region, (13), lies within substrate (10) and is spaced apart form the first doped region (11). Channel region (15) lies within substrate (10) and between first (11) and second (13) doped regions. Gate oxide layer (30) overlies substrate (10). Floating gate (40), to which there is no direct electrical connection, and which overlies substrate (10), is separated from substrate (10) by a thin layer of gate oxide (30) while control gate (60), to which there is direct electrical connection, is generally positioned over the floating gate with intergate oxide (50) therebetween.
In the structure shown in FIG. 1f, control gate (60) overlaps the channel region, (17), adjacent to channel (15) under the floating gate, (40). This structure is needed because when the cell is erased, it leaves a positive charge on the floating gate. As a result, the channel under the floating gate becomes inverted. The series MOS transistor (formed by the control gate over the channel region) is needed in order to prevent current flow from control gate to floating gate. The length of the transistor, that is the overlap of the control gate over the channel region (17) determines the cell performance. Furthermore, the shape of the edge (43) and, in particular, that of edge (47) can affect the programming of the cell. It is disclosed in this invention that the shape and size of edge (47) will affect the programming erase speed of the cell substantially. The relatively rounded shape that is found in conventional cells shown in FIG. 1g and which affects the erase speed adversely is the result of the commonly used process which is illustrated in FIGS. 1a-1f. 
In FIG. 1a, layer of gate oxide (30) is thermally grown over substrate (10) using conventional methods. Next, a first polysilicon layer (40) is formed followed by the deposition of nitride layer (50). A photoresist layer (60) is then spun over the substrate and then patterned with a floating gate pattern as shown in FIG. 1b, which in turn, is etched into the nitride layer (50) as shown in FIG. 1c. The photoresist layer, which is no longer needed, is removed. Next, the first polysilicon that is exposed in the pattern openings in the nitride layer is oxidized to form polyoxide (45) as shown in FIG. 1d. Subsequently, the nitride layer is removed where now polyoxide (45) serves as a hard mask to remove all the first polysilicon portions except those that are covered by the polyoxide (FIG. 1e). As is well known in the art, this is usually accomplished by main etch followed by over-etch. It is at this etching step that the corner edge (47) is usually rounded off, as seen in FIG. 1e, which is not desirable for achieving fast program erase speed described below. It will be shown later in the embodiments of this invention that by employing a different process step, the sharpness of corner edge (47) can be preserved such that charge transfer (33) between substrate (10) and floating gate (40), and then the charge transfer (53) between the floating gate and control gate, (60), is fast. The control gate is formed by depositing a second polysilicon layer over intergate layer (50), also known as interpoly, which separates the two polysilicon layers, namely, the floating polygate and the control polygate.
To program the transistor shown in FIG. 1f, charge is transferred from substrate (10) through gate oxide (30) and is stored on floating gate (40) of the transistor. The amount of charge is set to one of two levels to indicate whether the cell has been programmed “on” of “off.” “Reading” of the cell's state is accomplished by applying appropriate voltages to the cell source (11), Vs, drain (13), Vd, and to control gate (60), Vg, and then sensing the amount of charge on floating gate (40). To erase the contents of the cell, charges are removed from the floating gate by transferring them to the word line (control gate) through the gate oxide. The path of the charge transfer is shown by arrows (33) and (43) in FIG. 1f. 
This programming and erasing of an EEPROM is accomplished electrically and in-circuit by using Fowler-Nordheim (FN) tunneling for erasing, and channel-hot electron (CHE) injection for programming, as is well known in the art. FN tunneling usually requires higher voltage than the CHE mechanism. It is common practice use FN tunneling for both write and erase for NAND type of cell architecture, while CHE programming and FN tunneling erasure is used for NOR circuits. The latter approach is shown in FIG. 1f. Thus, in the programming mode, source (11) is coupled to the floating gate through a high voltage which in turn creates a high electric field between floating gate (40) and control gate (60), thereby causing injection of CHEs from substrate (10) to floating gate (40) in FIG. 1f. In the erase mode, on the other hand, the control gate is impressed with a high voltage and electrons are injected from the floating gate to the control gate through the FN tunneling mechanism, usually aided by the poly tip of the floating gate.
Several different methods of forming split-gate flash memory cells are described in prior art. Sung in U.S. Pat. No. 5,783,473 teaches a method of manufacturing a split gate flash memory unit where an asperity effect, which is said to cause a detrimental “point discharge” phenomenon, is minimized. A method of making a high density split gate nonvolatile memory cell is proposed by Hsia, et al., in U.S. Pat. No. 4,861,730 by providing a reduced channel length. Wang, on the other hand, shows a single-side oxide sealed salicide process for EEPROMs in U.S. Pat. No. 5,597,751. None of the cited prior art teaches a method to form, nor a structure having, a recess in a polysilicon layer to fabricate a floating gate containing a sloped edge region wherein a sharp poly tip is formed to improve the erase speed of a split gate flash memory cell. Such a method and structure are disclosed in the embodiments of this invention.